Grenoble Innovation for Advanced New Technologies

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    Revue GIANT : MICROELECTRONICS

    FD-SOI: a Competitive Solution for Next Generation Chips

     

     

     

    Nanotechnology is a major building block of the GIANT ecosystem with numerous platforms and research labs dedicated to both fundamental research and the transfer of technology. More than 20 years of research at the CEA-Leti has led to the creation and industrialization of Fully Depleted Silicon On Insulator (FD-SOI) technology – Grenoble’s answer to meet continuous demands for smaller chips with higher performance and lower energy consumption.

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    From the Internet of Things and wearables to the automotive or medical industries, better performance and energy efficiency are essential to produce the next generation of digital technology. One of the key challenges of nanotechnology has been to downscale the size of transistors, which are used in chips such as the one in your computer. Current semiconductor chips have been downscaled to the 14 nm limit. However, the process becomes all the more difficult as the industry aims to produce ten nanometer and smaller chips.

    BARRIERS TO DOWNSCALING
    Traditional methods for producing chips encountered severe difficulties upon reaching the 28 nm limit. « One of the main issues is that denser chips have a higher proportion of current leakage due to the fact that the more you downscale transistors, the more difficult it becomes to control the flow of current. » explains Thierry Poiroux, a researcher at the CEA-Leti (an institution that was highly involved in the development of FD-SOI technology).

    GODART/CEA
    GODART/CEA

    FD-SOI technology makes it possible to produce smaller transistors with lower leakage, and improved performance and energy consumption (see box – FD-SOI Research Focus).

    « The technology has demonstrated its capacity to meet demands for technology generations as small as 14 nm, which is the industry’s current technological limit. The challenge is to demonstrate the technology’s viability for next generation chips. » adds Poiroux.

    “Benchmarking studies demonstrate the viability of FD-SOI for ten nanometer chips”

    FD-SOI: A SOLUTION FOR TEN AND SEVEN NANOMETER CHIPS?
    While the industrialization of FD-SOI technology continues to advance for current generation chips, researchers at the CEA-Leti are already focused on the next two generations. « Current benchmarking studies have demonstrated that FD-SOI can at least be used for ten nanometer chips. However, as we downscale to the next generation, we must find innovative ways to boost performance. » explains Poiroux.
    The CEA-Leti‘s latest research is focused on increasing performance thanks to new mechanical stress techniques (see box: FD-SOI Research Focus) « FD-SOI technology relies on planar fabrication processes that are similar to traditional chip fabrication. By proving FD-SOI’s viability for next generation chips, we demonstrate that it is possible to achieve considerable performance and energy improvements without switching to more expensive fcea-capture-citationabrication techniques. » concludes Poiroux. Given the aggressive competition in the field of microprocessors, proving the viability of FD-SOI technology for current and next generation chips is an essential stake for the Grenoble ecosystem.

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